This invention relates to a digital signal processor evaluation chip (integrated circuit) and a debug method using this evaluation chip.
Digital signal processors (DSPs) are widely used in communication and image-processing equipment, to name only two of many applications. To assist in the debugging of DSP applications, manufacturers provide DSP evaluation chips adapted so that the user can halt program execution at an arbitrary address and examine the contents of internal DSP registers.
Prior-art evaluation chips comprise, for example, a clock control circuit For halting the DSP clock in response to a break signal, a step-execution control circuit for executing instructions one at a time during the break state, and a data bus monitor circuit for transferring data from an on-chip data bus to external emulator apparatus. To halt program execution and see register contents, the debugger sends the clock control circuit a break signal, then sends the step-execution control circuit a register data transfer instruction. This instruction causes register contents to be placed on the data bus, from which they can be read via the data bus monitor circuit.
The complexity of step-execution control circuits and clock control circuits, however, makes these prior-art evaluation chips difficult and costly to manufacture. In many cases the step execution function is-not needed. It would suffice to halt program execution at a selected address and view register contents, but the prior art provides no means of accomplishing tills in DSP chips without a step-execution control circuit.